Integrated circuits are often formed on a semiconductor substrate, such as a silicon wafer or other semiconductive material. In general, various materials such as semiconductive, conductive, or electrically insulative materials, are used to form integrated circuits. By way of example, the various materials may be doped, ion implanted, deposited, etched, grown, etc., using various processes. A continuing goal in semiconductor processing is to reduce the size of individual electronic components, thus enabling smaller and denser integrated circuitry.
One technique for patterning and processing semiconductor substrates is photolithography. Such technique includes deposition of a patternable masking layer commonly known as photoresist. These materials can be processed to modify their solubility in certain solvents, and are therefore readily used to form patterns on a substrate. For example, portions of a photoresist layer can be exposed to actinic energy through openings in a radiation-patterning tool, such as a mask or reticle, to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed regions can be removed, depending on the type of photoresist, to leave a masking pattern of the photoresist on the substrate. Adjacent areas of the underlying substrate next to the masked portions can be processed, for example by etching or ion implanting, to effect the intended processing of the substrate adjacent the masking material. In certain instances, multiple different layers of photoresist and/or a combination of photoresists with non-radiation sensitive masking materials are used. Further, patterns may be formed on substrates without using photoresist.
The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. As such, a need has arisen to more accurately define and control the dimensions and shapes of photoresist (resist) features used to pattern substrates. Various techniques have been developed to treat photoresist features after the photoresist features are formed, yet before the photoresist features are used to pattern a substrate. The treatment may be used, for example, to control the shape and roughness for photoresist features. Etch has been known to improve line edge roughness (LER) or line width roughness (LWR) during the patterning process, yet there exists a limit to how much etch can improve contact edge roughness (CER).
Furthermore, local critical dimension uniformity (LCDU) of contact holes becomes influential with continued scaling, resulting in variations in device performance and contributing to the total edge placement errors. LCDU of contact holes is generally influenced by a number of factors, including, yet not limited to: resist residue on feature sidewalls due to uneven acid concentration within the resist, an effect collectively known as “shot noise,” and irregularities during the development process; non-straight sidewalls and/or excessive footing at the bottom of the resist; and significant CER as a result of the shot noise.